A multiple power supply semiconductor large scale integration (LSI) includes a level shift circuit, which interconnects circuits having different power supply voltages (refer to, for example, Japanese Laid-Open Patent Publication Nos. 2005-252481, 05-283997, and 06-204850).
FIG. 17 illustrates one example of a conventional level shift circuit 120.
The level shift circuit 120 outputs an output signal So, which corresponds to an input signal Si. The gate of an N-channel MOS transistor TN11 is provided via an inverter circuit 121 with the input signal Si, which has the signal levels of a reference voltage GND and a first high potential voltage VL. The gate of an N-channel MOS transistor TN12 is provided with the input signal Si via the inverter circuit 121 and a further inverter circuit 122. Accordingly, the gates of the transistors TN11 and TN12 are provided with signals that are inverted from each other.
The drains of the transistors TN11 and TN12 are coupled to the drains of P-channel MOS transistors TP11 and TP12, respectively. The sources of the transistors TP11 and TP12 are supplied with a second high potential voltage VH, which is higher than the first high potential voltage VL. Further, the gate of the transistor TP11 is coupled to the drain of the transistor TP12, and the gate of the transistor TP12 is coupled to the drain of the transistor TP11. This forms a so-called cross-coupled connection (cross-connection). The output signal So is output via an inverter circuit 123 from a node N100 between the transistors TP11 and TP12.
In the level shift circuit 120, in response to an input signal Si having an H-level (first high potential voltage level VL), the transistor TN11 is inactivated and the transistor TN12 is activated. Subsequently, the transistor TP11 is activated and the transistor TP12 is inactivated. This outputs an output signal So having an H level (second high potential voltage level VH) from the inverter circuit 123.
When an input signal Si having an L level (reference voltage level GND) is input, the transistor TN11 is activated and the transistor TN12 is inactivated. Subsequently, the transistor TP11 is inactivated and the transistor TP12 is activated. This outputs an output signal So having an L level (reference voltage level GND) from the inverter circuit 123.
In this manner, the level shift circuit 120 converts the input signal Si, which has the signal levels of the reference voltage GND and the first high potential voltage VL, into the output signal So, which has signal levels of the reference voltage GND and the second high potential voltage VH.
The drains of the N-channel MOS transistors TN11 and TN12 are supplied with the second high potential voltage VH via the activated P-channel MOS transistors TP11 and TP12. Thus, a high withstand voltage corresponding to the second high potential voltage VH is set for the N-channel MOS transistors TN11 and TN12. The high-withstand voltage transistors TN11 and TN12 have a high threshold voltage. There is a recent trend of a decrease in the power supply voltage of semiconductor integrated circuits. Thus, the supply of the first high potential voltage VL to the transistors TN11 and TN12, which have high threshold voltages, may result in problems that arise as will now be described. When the first high potential voltage VL is close to the threshold voltage of the transistors TN11 and TN12, the first high potential voltage VL may not be able to activate the transistor TN12. In such a case, the transistor TN12 cannot generate a flow of current that is sufficient for lowering the voltage at node N100 to the reference voltage level GND. As a result, the level shift circuit 120 may fail to function properly.